In a conventional analog and mixed-signal design flow, the front-end design and the back-end design are performed independently in a sequential manner. A front-end circuit designer would hand off a size-optimized design to a back-end circuit designer to create the layout and its corresponding extracted netlist containing parasitic information of the circuit. As a result, the parasitic effects from the layout are not taken into account in the front-end design process. This design approach is particularly challenging for analog and mixed-signal designs because of the shrinking design cycles and aggressive performance specifications. As the analog and mixed-signal designs migrate to sub-micron and nanometer technologies, the layout parasitic information may significantly impact the circuit performances.
This conventional design flow is typically iterated multiple times until a desirable result is converged. In this approach, the designer first creates a sized design using the sizing tool. The computed device sizes determined by the sizing tool are then passed to the layout tool to create a layout. Alter that, an extractor tool is used to create an extracted netlist from the layout. The extracted netlist is then used by the sizing tool again to resize the design. In the conventional design flow, the parasitic information from the extracted netlist that is used by the sizing tool is derived from a previous layout of the design. The variations in device sizes often affect the placement and routing of the circuit, which in turn affect the layout parasitic information. In some situations, a designer may have to iterate multiple times before a desirable result can be achieved, resulting in an overall loss of time. In other situations, this deficiency causes designers to size the circuits over-conservatively, thus compromising the performance goals of the circuit.
Therefore, there is a need for an integrated sizing, layout, and extractor tool that can address the drawbacks of the various problems discussed above. The present invention describes a novel design methodology that integrates sizing, layout, and extractor tools to account for detailed layout parasitic information during the circuit sizing optimization process.